1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) and, more particularly, to stress applying means for applying voltage stress to word line groups more acceleratedly than a normal use at the time of screening defectiveness in a wafer state.
2. Description of the Related Art
A screening is generally performed to expose latent defects in semiconductor devices and remove from finished batches those devices having defects. This screening process prevents defect-free devices from being adversely affected by defective devices and ensures the reliability of the finished semiconductor devices when they are put on the market. As one screening method, a burn-in capable of accelerating an electric field and a temperature at the same time is frequently employed. In this burn-in, semiconductor devices are operated using a voltage higher than the actual working voltage and a temperature higher than the actual working temperature, and voltage stress is applied to the semiconductor devices for a short period of time longer than the initial failure period under actual working conditions. The semiconductor devices are then screened and those which are considered likely to malfunction in initial operation are removed. This type of screening is an efficient method of removing defective devices, thereby enhancing the reliability of finished semiconductor devices.
In recent DRAMs, a potential (for example, approximately 1.5.times.Vcc) boosted when a transfer gate (hereinafter referred to as cell transistor) of a selected memory cell is applied to a gate oxide film of the memory cell transistor. Even though the gate oxide film is thick, a strong electric field is applied thereto and thus the reliability of the DRAMs may be lowered. It is thus necessary to actively screen cell transistors having gates to which a boosted potential is applied when the burn-in of DRAMs is performed.
To screen the memory cells when the burn-in of the DRAMs is performed, a method of scanning an address so as to sequentially access word lines connected to the gates of the cell transistors was conventionally used. In this method, voltage stress is applied to the cell transistors less frequently than to transistors of a peripheral circuit and a time period for which the greatest electric field is actually applied to the cell transistors is short; accordingly, a long time is needed for the burn-in of DRAMs.
In order to eliminate the above drawback wherein the voltage stress is applied to the cell transistors less frequently, one of the inventors of the present invention proposed a semiconductor memory capable of improving in efficiency with which voltage stress is applied to cell transistors, as disclosed in Published Unexamined Japanese Patent Application (kokai) No. 3-35491 which corresponds to U.S. patent. application Ser. No. 07/544,614. The semiconductor memory is so formed that voltage stress can be applied to all word lines or word lines more than those selected in a normal operation mode when a defective cell transistor is screened.
If the above proposal is applied to a DRAM, defective cell transistors can considerably be reduced and 1M or 4M DRAMs having bit defects can be decreased at high speed by the screening. Therefore, the screening can be greatly improved in efficiency.
It is desirable to materialize a means for applying voltage stress to all word lines or word lines more than those selected in the normal operation mode when a operation power is supplied to the DRAMs.